1. Field of the Invention
The present invention relates to an optical signal reception device for receiving and demodulating optical signals modulated by a Differential Quadrature Phase Shift Keying (DQPSK) modulation scheme or a Differential Phase Shift Keying (DPSK) modulation scheme in order to achieve high speed data transmission, and a method of controlling reception of optical signals.
2. Description of the Related Art
In digital communication systems, typically the Internet (IP: Internet Protocol), in order to meet rapidly increasing needs of digital communication, an optical communication scheme employing IM-DQPSK (Intensity Modulation Differential Quadrature Phase Shift Keying) modulation scheme is being studied to improve utilization of frequencies.
For details of IM-DQPSK, reference can be made to P. S. Cho, V. S. Grigoryan, Y. A. Godin, A. Salamon, and Y. Achiam, “Transmission of 25 Gbps RZ-DQPSK signals with 25-GHz channel spacing over 1000 km of SMF-28 fiber”, IEEE Photonic Technical Letter, Vol. 15, pp. 473-475, March 2003 (hereinafter, referred to as “reference 1”), and H. Kim, and R-J. Essiambre, “Transmission of 8×20 Gbps DQPSK signals with 25-GHz channel spacing over a 310-km SMF with 0.8-b/s/Hz spectral efficiency”, IEEE Photonic Technical Letter, Vol. 15, pp. 769-771, May, 2003 (hereinafter, referred to as “reference 2”).
FIG. 38 is a block diagram illustrating an optical transponder (an optical sender and an optical receiver) employing the above IM-DQPSK modulation scheme.
The optical transponder illustrated in FIG. 38 includes a framer LSI 100, an optical receiver (40 G OR) 101, a serializer (SER) 102, a de-multiplexer (DEMUX) 103, a DQPSK precoder 104, a DQPSK modulator (40 G OS DQPSK) 105, a DQPSK optical sender (40 G OS) 106, a de-serializer (DES) 107, a multiplexer (MUX) 108, and a DQPSK demodulator (40 G OR DQPSK) 109.
The DQPSK modulator 105, as schematically exemplified in an expanded portion thereabove in FIG. 38, includes a DFB-LD (Distributed Feedback Laser), a phase modulation section 112, an intensity modulator 113, and a driver. The phase modulation section 112 includes phase modulators 114, 115 and a π/2 phase shifter.
The DQPSK demodulator 109, as schematically exemplified in an expanded portion therebelow in FIG. 38, includes a π/4 delay interferometer 116, a −π/4 delay interferometer 117, photo-diodes (PDs) acting as opto-electric conversion elements, and amplifiers (amp). It should be noted that the configuration of the DQPSK demodulator 109 in FIG. 38 as described above illustrates a state in which the optical transmission direction is reversed.
In FIG. 38, it is illustrated that the transponder converts data signals transmitted at a bit rate of 40 Gbps into optical signals, modulates the optical signals by the DQPSK modulation scheme, and transmits the signals.
As illustrated in FIG. 38, the optical receiver 101 receives the optical signals transmitted at a bit rate of 40 Gbps from a client (user) side, converts the optical signals into electrical signals, and outputs 16 parallel signals each at a bit rate of 2.5 Gbps (=40 Gbps/16) to the framer LSI 100.
The framer LSI 100 transforms each of the 16 parallel signals from the optical receiver 101 into multiple frames, and performs mapping and de-mapping on each frame by means of, for example, SONET (Synchronous Optical Network), SDH (Synchronous Digital Hierarchy), or OTN (Optical Transport Network). In this figure, it is assumed that the framer LSI 100 is the one for OTN.
After the frame processing, the framer LSI 100 outputs 16 parallel signals each at 2.7 Gbps.
A serializer 102 converts the 16 parallel signals at a bit rate of 2.7 Gbps from the framer LSI 100 into a serial data signal at 43 Gbps.
The de-multiplexer (DEMUX) 103 receives the serial data signal at 43 Gbps and a clock signal (CLK) at 21.5 GHz, de-multiplexes the signals from the serializer 102 at a de-multiplexing ratio of 1 to 2, and generates two parallel signals Ik and Qk each at 21.5 Gbps.
The signals Ik and Qk output from the de-multiplexer (DEMUX) 103 are input to the DQPSK precoder 104. The DQPSK precoder 104 converts the signals Ik and Qk into signals ρk and ηk, and inputs the obtained signals ρk and ηk to the DQPSK demodulator 105.
The DQPSK precoder 104 converts the input in-phase signals Ik and quadrature-phase signals Qk into signals ρk and ηk according to the following logical relations.
                              ρ          k                =                                            Q              k                        ⁢                          ρ                              k                -                1                                      ⁢                          η                              k                -                1                                              +                                    I              k                        ⁢                          ρ                              k                -                1                                      ⁢                                          η                                  k                  -                  1                                            _                                +                                                                      I                  k                                ⁢                                  ρ                                      k                    -                    1                                                  ⁢                η                            _                                      k              -              1                                +                                                    Q                k                            ⁢                              ρ                                  k                  -                  1                                            ⁢                              η                                  k                  -                  1                                                      _                                                            η          k                =                                            I              k                        ⁢                          ρ                              k                -                1                                      ⁢                          η                              k                -                1                                              +                                                    Q                k                            _                        ⁢                          ρ                              k                -                1                                      ⁢                                          η                                  k                  -                  1                                            _                                +                                    Q              k                        ⁢                                                                                ρ                                          k                      -                      1                                                        ⁢                  η                                _                                            k                -                1                                              +                                                    I                k                            ⁢                              ρ                                  k                  -                  1                                            ⁢                              η                                  k                  -                  1                                                      _                              
FIG. 39 is a circuit diagram illustrating an example of a configuration of the DQPSK precoder 104.
As illustrated in FIG. 39, the DQPSK precoder 104 may be a logic gate circuit constructed by combining logical OR circuits, logical AND circuits, and inhibit circuits or other kinds of logic circuits. In FIG. 39, “D” indicates a one-bit delay circuit.
The signals ρk and ηk (at 21.5 Gbps) encoded by the DQPSK precoder 104 are input to the DQPSK modulator 105. The DQPSK modulator 105 converts the signals ρk and ηk into DQPSK optical signals and sends the optical signals to the network side.
The DQPSK modulator 105 splits a light beam emitted from the DFB-LD 111 into two beams, outputs one of the two split light beams into the phase modulator 114, and shifts the phase of the other split light beam by π/2 and outputs the phase-shifted light beam into the phase modulator 115. The phase modulators 114 and 115 perform phase modulation on the respective input light beams according to the respective signals ρk and ηk from the precoder 104 at 21.5 Gbps. The output light beams from the phase modulators 114 and 115 are combined and are input to the intensity modulator 113. The intensity modulator 113 performs intensity modulation on the input optical signals according to the clock signal (clock) at 21.5 GHz, and generates and transmits IM-DQPSK optical signals at 43 Gbps.
For example, each of the phase modulators 114 and 115, and the intensity modulator 113 of the DQPSK modulator 105 may be structured by a Mach-Zehnder interferometer formed by elements having the electro-optical effect, such as LiNbO3.
The DQPSK demodulator 109 receives the DQPSK optical signals from the network side, splits the optical signals into two portions, outputs one portion into the π/4 delay interferometer 116, delays the phase of the other portion by −π/4, and outputs the resulting optical signals into the −π/4 delay interferometer 117.
Each of the delay interferometers 116 and 117, for example, generates a path length difference between two path lengths each being constituted by a light guide, and generates a time delay τ corresponding to one symbol of the modulated optical signal.
The delay interferometer 116 has a π/4 phase shifter in an arm thereof for generating a π/4 phase shift, and the delay interferometer 117 has a −π/4 phase shifter in an arm thereof for generating a −π/4 phase shift.
Optical signals from arms of the delay interferometers 116 and 117 enter a pair of photo detectors (PD) as light receiving elements via couplers at the output stages of the delay interferometers 116 and 117, and after opto-electric conversion, an in-phase signal Ik is output from the side of the delay interferometer 116, and an quadrature-phase signal Qk is output from the side of the delay interferometer 117.
The multiplexer (MUX) 108 multiplexes the data signals Ik and Qk from the DQPSK optical demodulator 109 at 21.5 Gbps to convert the data signals Ik and Qk into a serial data signal at about 43 Gbps, and outputs the serial data signal at about 43 Gbps and the clock signal (clock) at 21.5 GHz to the de-serializer (DES) 107 in parallel.
The de-serializer 107 converts the serial data signal at about 43 Gbps into 16 parallel signals each at about 2.7 Gbps, and outputs the resulting signals into the framer LSI 100.
The framer LSI 100 de-maps the SONET, SDH or OTN frames, obtains 16 parallel signals each at about 2.5 Gbps, and outputs the 16 parallel signals to the optical sender 106.
The optical sender 106 converts the 16 parallel signals into a serial optical signal, and sends the optical signal at about 43 Gbps to the client side.
In addition, it is proposed to use Mach-Zehnder type delay interferometers in DMPSK (Differential Multiple Phase Shift Keying) optical signal modulation and demodulation unit with M=2n. For example, such an optical communication system is disclosed in International Application's Japanese Publication No. 2004-516743, in which the DMPSK modulation scheme becomes the same as the above DQPSK modulation scheme when n=2.
In addition, for example, an optical communication system is disclosed in International Application's Japanese Publication No. 2004-533163, in which a phase-modulated optical signal is intensity-modulated by a clock signal and is then transmitted; on a receiver end, the clock signal is recovered based on the intensity-modulated component.
FIG. 40 is a block diagram illustrating a principal portion of an optical signal receiver used in an optical communication system for transmitting the DQPSK optical signals.
Illustrated in FIG. 40 are a front end 121 (40 G DQPSK OR), a clock and data recovery (20 G CDR A) 123, a clock and data recovery (20 G CDR B) 124, a multiplexer (MUX) 126, a de-serializer (DES) 128, and a framer LSI 129 acting as a frame processing unit.
In FIG. 40, the direction of the signal flow is opposite to the path of signal reception processing in FIG. 38, but the functions of processing are the same.
Specifically, the front end 121 corresponds to the DQPSK demodulator 109 in FIG. 38.
The multiplexer 126 multiplexes the signals output from each of the clock and data recovery 123 and the clock and data recovery 124 at a multiplexing ratio of 2:1.
The de-serializer (DES) 128 converts the input signals into 16 parallel signals each at 2.7 Gbps.
The framer LSI 129 receives 16 parallel signals each at 2.7 Gbps, and has the same de-mapping functions as the framer 100 in FIG. 38.
The in-phase signal component Ik and the quadrature-phase signal component Qk are output from a port A and a port B of the front end 121. However, when DQPSK optical signals are transmitted through an optical transmission path, waveforms of the optical signals may be degraded because of influences of wavelength dispersion and the non-linear effect of the optical fiber in use. In addition, because the two interferometers of the front end 121 are independent from each other, if the optimum operating points of the two interferometers change with age or due to temperature changes, probably, the signal Ik and the signal Qk satisfying desired logical relations cannot be obtained.
FIG. 41 is a block diagram illustrating principal portions of an optical signal receiver side and an optical signal transmitter side of the optical transponder as shown in FIG. 38.
The structure shown in FIG. 41 includes a transmission processing unit 421 (indicated as “OTN LSI” in FIG. 41), an optical modulation processing unit 422 (indicated as “43 G NB Mod (Tx side)”), an optical signal reception processing unit 423 (indicated as “43 G NB Mod (Rx side)”), and a reception processing unit 424 (indicated as “OTN LSI”).
In FIG. 41, an SFI-5 interface is a parallel signal interface for connecting the transmission processing unit 421 and the optical modulation processing unit 422, and for connecting the optical signal reception processing unit 423 and the reception processing unit 424; the SFI-5 interface is in compliance with a 40 Gbps Serdes Framer Interface standard established by OIF-SFI5-01.02 of OIF (Optical Interface Forum).
It should be noted that the parallel signal interface for connecting the transmission processing unit 421 and the optical modulation processing unit 422, and for connecting the optical signal reception processing unit 423 and the reception processing unit 424 is not limited to the SFI-5 interface, but can be other similar signal interfaces.
The transmission processing unit 421 includes a framer and others, and the optical modulation processing unit 422 includes a serializer (SER), a de-multiplexer (1:2 DEMUX), a driver which receives data ηk, and ρk for controlling a phase modulator, a DFB-LD (Distributed Feedback Semiconductor Laser), and an intensity modulator. RZ-DQPSK optical signals output from the intensity modulator are transmitted as data at time k, k+1, k+2, . . . along the time axis, and are indicated as {Ik, Qk}, {Ik+1, Qk+2}, . . . .
The optical signal reception processing unit 423 includes a π/4 delay interferometer, a −π/4 delay interferometer, photo-diodes (PDs) acting as opto-electric conversion elements, amplifiers (amp), a multiplexing processing unit CDR+2:1MUX for reproducing clocks and data and for multiplexing, and a de-serializer (DES), which corresponds to the structure in FIG. 38 including the π/4 delay interferometer 116, the −π/4 delay interferometer 117, the photo-diodes (PDs), the amplifiers (amp), the multiplexer (MUX) 108, and the de-serializer (DES) 107.
Each of the multiplexing processing unit CDR+2:1MUX and the de-serializer (DES) is an integrated circuit.
The reception processing unit 424 corresponds to the framer 100 and the DQPSK optical sender 106 in FIG. 38.
In the optical signal reception processing unit 423, signals Ak, Ak+1, . . . obtained by opto-electric conversion from the π/4 delay interferometer, and signals Bk, Bk+1, . . . obtained by opto-electric conversion from the −π/4 delay interferometer are multiplexed by the multiplexing processing unit CDR+2:1MUX, resulting in signals Ak, Bk, Ak+1, Bk+1, . . . , and the signals Ak, Bk, Ak+1, Bk+1, . . . are transmitted to the de-serializer (DES); the de-serializer (DES) converts the signals Ak, Bk, Ak+1, Bk+1, . . . into 16 parallel signals, and transmits the 16 parallel signals to the reception processing unit 424 including a framer via the SFI-5 interface. Depending on the timing of the serial-parallel conversion, the order of the 16 parallel signals may be determined according to a combination of a case 1 and a case 2 as shown in FIG. 41, or a combination of a case 3 and a case 4 as shown in FIG. 41.
FIG. 42A through FIG. 42C are tables illustrating reception states in portions (a), (b), and (c) in FIG. 41.
FIG. 42A illustrates reception states of the optical signal reception processing unit 423 with A channel (Ach) signals and B channel (Bch) signals under various conditions.
In the table in FIG. 42A, for example, a double circle indicates an object signal reception state, single circles indicate that either the A channel signal or the B channel signal or both of them are in a logical inversion state relative to the object signal reception state, triangles indicate a state generated by logical inversion and bit swap, a diamond indicates a state of bit swap, and crosses indicates states not allowing signal reception such as synchronization pull-in state.
FIG. 42B and FIG. 42C illustrate reception states of a 16-parallel signal interface between the de-serializer (DES) and the reception processing unit 424.
Depending on the opto-electric conversion, clock/data regeneration (clock and data recovery) and multiplexing, and the order of signals output from the de-serializer (DES), the reception state becomes one of case 1 through case 4, and the case 3 and case 4 correspond to one-bit shifted situation relative to the case 1 and case 2. For this reason, FIG. 42B represents reception states corresponding to the case 1 and case 2, and FIG. 42C represents reception states corresponding to the case 3 and case 4. In FIG. 42B and FIG. 42C, if double circles indicate object signal reception states, as in FIG. 42A, reception states represented by single circles, triangles, diamonds, and crosses occur.
As described above, in the object signal reception state, which is represented by the double circle, an optical signal reception process can be performed normally, and frame synchronization can be established. However, in states other than the object signal reception state, the frame pull-in process cannot be performed, and hence, a normal signal reception process cannot be performed.
In addition, even when functions of components of the device are specified in detail to designate the object signal reception state when initially starting the device, operation conditions of the components may change with age or with temperature changes, and in this case, one has to set the conditions of the components again.